The PCIe hotlink is congenital about committed unidirectional couples of afterwards (1-bit), point-to-point admission accepted as lanes. This is in aciculate adverse to the beforehand PCI connection, which is a bus-based arrangement area all the accessories allotment the aforementioned bidirectional, 32-bit or 64-bit alongside bus.
PCI Accurate is a layered protocol, consisting of a transaction layer, a abstracts hotlink layer, and a concrete layer. The Abstracts Hotlink Band is subdivided to cover a media admission ascendancy (MAC) sublayer. The Concrete Band is subdivided into analytic and electrical sublayers. The Concrete logical-sublayer contains a concrete coding sublayer (PCS). The agreement are adopted from the IEEE 802 networking agreement model.
edit Concrete layer
The PCIe Concrete Band (PHY, PCIEPHY, PCI Accurate PHY, or PCIe PHY) blueprint is disconnected into two sub-layers, agnate to electrical and analytic specifications. The analytic sublayer is sometimes added disconnected into a MAC sublayer and a PCS, although this analysis is not formally allotment of the PCIe specification. A blueprint appear by Intel, the PHY Interface for PCI Accurate (PIPE),25 defines the MAC/PCS anatomic administration and the interface amid these two sub-layers. The PIPE blueprint aswell identifies the concrete media adapter (PMA) layer, which includes the serializer/deserializer (SerDes) and added analog circuitry; however, back SerDes implementations alter abundantly a part of ASIC vendors, PIPE does not specify an interface amid the PCS and PMA.
At the electrical level, anniversary lane consists of two unidirectional LVDS or PCML pairs at 2.525 Gbit/s. Address and accept are abstracted cogwheel pairs, for a absolute of 4 abstracts affairs per lane.
A affiliation amid any two PCIe accessories is accepted as a link, and is congenital up from a accumulating of 1 or added lanes. All accessories have to minimally abutment single-lane (×1) link. Accessories may optionally abutment added links composed of 2, 4, 8, 12, 16, or 32 lanes. This allows for actual acceptable affinity in two ways:
A PCIe agenda physically fits (and works correctly) in any aperture that is at atomic as ample as it is (e.g., an ×1 sized agenda will plan in any sized slot);
A aperture of a ample concrete admeasurement (e.g., ×16) can be active electrically with beneath lanes (e.g., ×1, ×4, ×8, or ×12) as continued as it provides the arena admission appropriate by the beyond concrete aperture size.
In both cases, PCIe negotiates the accomplished mutually accurate bulk of lanes. Many cartoon cards, motherboards and bios versions are absolute to abutment ×1, ×4, ×8 and ×16 connectivity on the aforementioned connection.
Even admitting the two would be signal-compatible, it is not usually accessible to abode a physically beyond PCIe agenda (e.g., a ×16 sized card) into a abate aperture —though if the PCIe slots are open-ended, by architecture or by hack, some motherboards will acquiesce this.citation needed
The amplitude of a PCIe adapter is 8.8 mm, while the acme is 11.25 mm, and the breadth is variable. The anchored area of the adapter is 11.65 mm in breadth and contains 2 rows of 11 (22 pins total), while the breadth of the added area is capricious depending on the bulk of lanes. The pins are spaced at 1 mm intervals, and the array of the agenda traveling into the adapter is 1.8 mm.2627
Lanes Pins Length
Total Variable Total Variable
×1 2×18 = 3628 2×7 = 14 25 mm 7.65 mm
×4 2×32 = 64 2×21 = 42 39 mm 21.65 mm
×8 2×49 = 98 2×38 = 76 56 mm 38.65 mm
×16 2×82 = 164 2×71 = 142 89 mm 71.65 mm
edit Abstracts transmission
PCIe sends all ascendancy messages, including interrupts, over the aforementioned links acclimated for data. The afterwards agreement can never be blocked, so cessation is still commensurable to accepted PCI, which has committed arrest lines.
Data transmitted on multiple-lane links is interleaved, acceptation that anniversary alternating byte is beatific down alternating lanes. The PCIe blueprint refers to this interleaving as abstracts striping. While acute cogent accouterments complication to accord (or deskew) the admission striped data, striping can decidedly abate the cessation of the nth byte on a link. Due to added requirements, striping may not necessarily abate the cessation of baby abstracts packets on a link.
As with added top abstracts bulk afterwards manual protocols, clocking advice is anchored in the signal. At the concrete level, PCI Accurate 2.0 utilizes the 8b/10b encoding scheme20 to ensure that strings of afterwards ones or afterwards zeros are bound in length. This was acclimated to anticipate the receiver from accident clue of area the bit edges are. In this coding arrangement every 8 (uncoded) burden $.25 of abstracts are replaced with 10 (encoded) $.25 of address data, causing a 20% aerial in the electrical bandwidth. To advance the accessible bandwidth, PCI Accurate adaptation 3.0 employs 128b/130b encoding instead: agnate but with abundant lower overhead.
Many added protocols (such as SONET) use a altered anatomy of encoding accepted as scrambling to bury alarm advice into abstracts streams. The PCIe blueprint aswell defines a scrambling algorithm, but it is acclimated to abate electromagnetic arrest (EMI) by preventing repeating abstracts patterns in the transmitted abstracts stream.
edit Abstracts hotlink layer
The Abstracts Hotlink Band performs three basic casework for the PCIe accurate link:
arrangement the transaction band packets (TLPs) that are generated by the transaction layer,
ensure reliable supply of TLPs amid two endpoints via an accepting agreement (ACK and NAK signaling) that absolutely requires epitomize of unacknowledged/bad TLPs,
initialize and administer breeze ascendancy credits
On the address side, the abstracts hotlink band generates an incrementing arrangement bulk for anniversary approachable TLP. It serves as a different identification tag for anniversary transmitted TLP, and is amid into the attack of the approachable TLP. A 32-bit circadian back-up analysis cipher (known in this ambience as Hotlink CRC or LCRC) is aswell added to the end of anniversary approachable TLP.
On the accept side, the accustomed TLP's LCRC and arrangement bulk are both accurate in the hotlink layer. If either the LCRC analysis fails (indicating a abstracts error), or the sequence-number is out of ambit (non-consecutive from the endure accurate accustomed TLP), again the bad TLP, as able-bodied as any TLPs accustomed afterwards the bad TLP, are advised invalid and discarded. The receiver sends a abrogating accepting bulletin (NAK) with the sequence-number of the invalid TLP, requesting re-transmission of all TLPs advanced of that sequence-number. If the accustomed TLP passes the LCRC analysis and has the actual arrangement number, it is advised as valid. The hotlink receiver increments the sequence-number (which advance the endure accustomed acceptable TLP), and assiduously the accurate TLP to the receiver's transaction layer. An ACK bulletin is beatific to bound transmitter, advertence the TLP was auspiciously accustomed (and by extension, all TLPs with accomplished sequence-numbers.)
If the transmitter receives a NAK message, or no accepting (NAK or ACK) is accustomed until a abeyance aeon expires, the transmitter have to retransmit all TLPs that abridgement a absolute accepting (ACK). Barring a assiduous malfunction of the accessory or manual medium, the link-layer presents a reliable affiliation to the transaction layer, back the manual agreement ensures supply of TLPs over an capricious medium.
In accession to sending and accepting TLPs generated by the transaction layer, the data-link band aswell generates and consumes DLLPs, abstracts hotlink band packets. ACK and NAK signals are announced via (DLLP), as are breeze ascendancy acclaim information, some ability administration letters and breeze ascendancy acclaim advice (on annual of the transaction layer.)
In practice, the bulk of in-flight, bearding TLPs on the hotlink is bound by two factors: the admeasurement of the transmitter's epitomize absorber (which have to abundance a archetype of all transmitted TLPs until they the bound receiver ACKs them), and the breeze ascendancy credits issued by the receiver to a transmitter. PCI Accurate requires all receivers to affair a minimum bulk of credits, to agreement a hotlink allows sending PCIConfig TLPs and bulletin TLPs.
edit Transaction layer
PCI Accurate accouterments breach affairs (transactions with appeal and acknowledgment afar by time), acceptance the hotlink to backpack added cartage while the ambition accessory gathers abstracts for the response.
PCI Accurate uses credit-based breeze control. In this scheme, a accessory advertises an antecedent bulk of acclaim for anniversary accustomed absorber in its transaction layer. The accessory at the adverse end of the link, if sending affairs to this device, counts the bulk of credits anniversary TLP consumes from its account. The sending accessory may alone address a TLP if accomplishing so does not accomplish its captivated acclaim adding beat its acclaim limit. If the accepting accessory finishes processing the TLP from its buffer, it signals a acknowledgment of credits to the sending device, which increases the acclaim absolute by the able amount. The acclaim counters are modular counters, and the allegory of captivated credits to acclaim absolute requires modular arithmetic. The advantage of this arrangement (compared to added methods such as delay states or handshake-based alteration protocols) is that the cessation of acclaim acknowledgment does not affect performance, provided that the acclaim absolute is not encountered. This acceptance is about met if anniversary accessory is advised with able absorber sizes.
PCIe 1.x is generally quoted to abutment a abstracts bulk of 250 MB/s in anniversary direction, per lane. This amount is a adding from the concrete signaling bulk (2.5 Gbaud) disconnected by the encoding aerial (10 $.25 per byte.) This agency a sixteen lane (×16) PCIe agenda would again be apparently able of 16×250 MB/s = 4 GB/s in anniversary direction. While this is actual in agreement of abstracts bytes, added allusive calculations are based on the accessible abstracts burden rate, which depends on the contour of the traffic, which is a action of the high-level (software) appliance and average agreement levels.
Like added top abstracts bulk afterwards interconnect systems, PCIe has a agreement and processing aerial due to the added alteration robustness (CRC and acknowledgements). Continued affiliated unidirectional transfers (such as those archetypal in high-performance accumulator controllers) can access >95% of PCIe's raw (lane) abstracts rate. These transfers aswell account the a lot of from added bulk of lanes (×2, ×4, etc.) But in added archetypal applications (such as a USB or Ethernet controller), the cartage contour is characterized as abbreviate abstracts packets with common activated acknowledgements.29 This blazon of cartage reduces the ability of the link, due to aerial from packet parsing and affected interrupts (either in the device's host interface or the PC's CPU.) Being a agreement for accessories affiliated to the aforementioned printed ambit board, it does not crave the aforementioned altruism for manual errors as a agreement for advice over best distances, and thus, this accident of ability is not accurate to PCIe.
PCI Accurate is a layered protocol, consisting of a transaction layer, a abstracts hotlink layer, and a concrete layer. The Abstracts Hotlink Band is subdivided to cover a media admission ascendancy (MAC) sublayer. The Concrete Band is subdivided into analytic and electrical sublayers. The Concrete logical-sublayer contains a concrete coding sublayer (PCS). The agreement are adopted from the IEEE 802 networking agreement model.
edit Concrete layer
The PCIe Concrete Band (PHY, PCIEPHY, PCI Accurate PHY, or PCIe PHY) blueprint is disconnected into two sub-layers, agnate to electrical and analytic specifications. The analytic sublayer is sometimes added disconnected into a MAC sublayer and a PCS, although this analysis is not formally allotment of the PCIe specification. A blueprint appear by Intel, the PHY Interface for PCI Accurate (PIPE),25 defines the MAC/PCS anatomic administration and the interface amid these two sub-layers. The PIPE blueprint aswell identifies the concrete media adapter (PMA) layer, which includes the serializer/deserializer (SerDes) and added analog circuitry; however, back SerDes implementations alter abundantly a part of ASIC vendors, PIPE does not specify an interface amid the PCS and PMA.
At the electrical level, anniversary lane consists of two unidirectional LVDS or PCML pairs at 2.525 Gbit/s. Address and accept are abstracted cogwheel pairs, for a absolute of 4 abstracts affairs per lane.
A affiliation amid any two PCIe accessories is accepted as a link, and is congenital up from a accumulating of 1 or added lanes. All accessories have to minimally abutment single-lane (×1) link. Accessories may optionally abutment added links composed of 2, 4, 8, 12, 16, or 32 lanes. This allows for actual acceptable affinity in two ways:
A PCIe agenda physically fits (and works correctly) in any aperture that is at atomic as ample as it is (e.g., an ×1 sized agenda will plan in any sized slot);
A aperture of a ample concrete admeasurement (e.g., ×16) can be active electrically with beneath lanes (e.g., ×1, ×4, ×8, or ×12) as continued as it provides the arena admission appropriate by the beyond concrete aperture size.
In both cases, PCIe negotiates the accomplished mutually accurate bulk of lanes. Many cartoon cards, motherboards and bios versions are absolute to abutment ×1, ×4, ×8 and ×16 connectivity on the aforementioned connection.
Even admitting the two would be signal-compatible, it is not usually accessible to abode a physically beyond PCIe agenda (e.g., a ×16 sized card) into a abate aperture —though if the PCIe slots are open-ended, by architecture or by hack, some motherboards will acquiesce this.citation needed
The amplitude of a PCIe adapter is 8.8 mm, while the acme is 11.25 mm, and the breadth is variable. The anchored area of the adapter is 11.65 mm in breadth and contains 2 rows of 11 (22 pins total), while the breadth of the added area is capricious depending on the bulk of lanes. The pins are spaced at 1 mm intervals, and the array of the agenda traveling into the adapter is 1.8 mm.2627
Lanes Pins Length
Total Variable Total Variable
×1 2×18 = 3628 2×7 = 14 25 mm 7.65 mm
×4 2×32 = 64 2×21 = 42 39 mm 21.65 mm
×8 2×49 = 98 2×38 = 76 56 mm 38.65 mm
×16 2×82 = 164 2×71 = 142 89 mm 71.65 mm
edit Abstracts transmission
PCIe sends all ascendancy messages, including interrupts, over the aforementioned links acclimated for data. The afterwards agreement can never be blocked, so cessation is still commensurable to accepted PCI, which has committed arrest lines.
Data transmitted on multiple-lane links is interleaved, acceptation that anniversary alternating byte is beatific down alternating lanes. The PCIe blueprint refers to this interleaving as abstracts striping. While acute cogent accouterments complication to accord (or deskew) the admission striped data, striping can decidedly abate the cessation of the nth byte on a link. Due to added requirements, striping may not necessarily abate the cessation of baby abstracts packets on a link.
As with added top abstracts bulk afterwards manual protocols, clocking advice is anchored in the signal. At the concrete level, PCI Accurate 2.0 utilizes the 8b/10b encoding scheme20 to ensure that strings of afterwards ones or afterwards zeros are bound in length. This was acclimated to anticipate the receiver from accident clue of area the bit edges are. In this coding arrangement every 8 (uncoded) burden $.25 of abstracts are replaced with 10 (encoded) $.25 of address data, causing a 20% aerial in the electrical bandwidth. To advance the accessible bandwidth, PCI Accurate adaptation 3.0 employs 128b/130b encoding instead: agnate but with abundant lower overhead.
Many added protocols (such as SONET) use a altered anatomy of encoding accepted as scrambling to bury alarm advice into abstracts streams. The PCIe blueprint aswell defines a scrambling algorithm, but it is acclimated to abate electromagnetic arrest (EMI) by preventing repeating abstracts patterns in the transmitted abstracts stream.
edit Abstracts hotlink layer
The Abstracts Hotlink Band performs three basic casework for the PCIe accurate link:
arrangement the transaction band packets (TLPs) that are generated by the transaction layer,
ensure reliable supply of TLPs amid two endpoints via an accepting agreement (ACK and NAK signaling) that absolutely requires epitomize of unacknowledged/bad TLPs,
initialize and administer breeze ascendancy credits
On the address side, the abstracts hotlink band generates an incrementing arrangement bulk for anniversary approachable TLP. It serves as a different identification tag for anniversary transmitted TLP, and is amid into the attack of the approachable TLP. A 32-bit circadian back-up analysis cipher (known in this ambience as Hotlink CRC or LCRC) is aswell added to the end of anniversary approachable TLP.
On the accept side, the accustomed TLP's LCRC and arrangement bulk are both accurate in the hotlink layer. If either the LCRC analysis fails (indicating a abstracts error), or the sequence-number is out of ambit (non-consecutive from the endure accurate accustomed TLP), again the bad TLP, as able-bodied as any TLPs accustomed afterwards the bad TLP, are advised invalid and discarded. The receiver sends a abrogating accepting bulletin (NAK) with the sequence-number of the invalid TLP, requesting re-transmission of all TLPs advanced of that sequence-number. If the accustomed TLP passes the LCRC analysis and has the actual arrangement number, it is advised as valid. The hotlink receiver increments the sequence-number (which advance the endure accustomed acceptable TLP), and assiduously the accurate TLP to the receiver's transaction layer. An ACK bulletin is beatific to bound transmitter, advertence the TLP was auspiciously accustomed (and by extension, all TLPs with accomplished sequence-numbers.)
If the transmitter receives a NAK message, or no accepting (NAK or ACK) is accustomed until a abeyance aeon expires, the transmitter have to retransmit all TLPs that abridgement a absolute accepting (ACK). Barring a assiduous malfunction of the accessory or manual medium, the link-layer presents a reliable affiliation to the transaction layer, back the manual agreement ensures supply of TLPs over an capricious medium.
In accession to sending and accepting TLPs generated by the transaction layer, the data-link band aswell generates and consumes DLLPs, abstracts hotlink band packets. ACK and NAK signals are announced via (DLLP), as are breeze ascendancy acclaim information, some ability administration letters and breeze ascendancy acclaim advice (on annual of the transaction layer.)
In practice, the bulk of in-flight, bearding TLPs on the hotlink is bound by two factors: the admeasurement of the transmitter's epitomize absorber (which have to abundance a archetype of all transmitted TLPs until they the bound receiver ACKs them), and the breeze ascendancy credits issued by the receiver to a transmitter. PCI Accurate requires all receivers to affair a minimum bulk of credits, to agreement a hotlink allows sending PCIConfig TLPs and bulletin TLPs.
edit Transaction layer
PCI Accurate accouterments breach affairs (transactions with appeal and acknowledgment afar by time), acceptance the hotlink to backpack added cartage while the ambition accessory gathers abstracts for the response.
PCI Accurate uses credit-based breeze control. In this scheme, a accessory advertises an antecedent bulk of acclaim for anniversary accustomed absorber in its transaction layer. The accessory at the adverse end of the link, if sending affairs to this device, counts the bulk of credits anniversary TLP consumes from its account. The sending accessory may alone address a TLP if accomplishing so does not accomplish its captivated acclaim adding beat its acclaim limit. If the accepting accessory finishes processing the TLP from its buffer, it signals a acknowledgment of credits to the sending device, which increases the acclaim absolute by the able amount. The acclaim counters are modular counters, and the allegory of captivated credits to acclaim absolute requires modular arithmetic. The advantage of this arrangement (compared to added methods such as delay states or handshake-based alteration protocols) is that the cessation of acclaim acknowledgment does not affect performance, provided that the acclaim absolute is not encountered. This acceptance is about met if anniversary accessory is advised with able absorber sizes.
PCIe 1.x is generally quoted to abutment a abstracts bulk of 250 MB/s in anniversary direction, per lane. This amount is a adding from the concrete signaling bulk (2.5 Gbaud) disconnected by the encoding aerial (10 $.25 per byte.) This agency a sixteen lane (×16) PCIe agenda would again be apparently able of 16×250 MB/s = 4 GB/s in anniversary direction. While this is actual in agreement of abstracts bytes, added allusive calculations are based on the accessible abstracts burden rate, which depends on the contour of the traffic, which is a action of the high-level (software) appliance and average agreement levels.
Like added top abstracts bulk afterwards interconnect systems, PCIe has a agreement and processing aerial due to the added alteration robustness (CRC and acknowledgements). Continued affiliated unidirectional transfers (such as those archetypal in high-performance accumulator controllers) can access >95% of PCIe's raw (lane) abstracts rate. These transfers aswell account the a lot of from added bulk of lanes (×2, ×4, etc.) But in added archetypal applications (such as a USB or Ethernet controller), the cartage contour is characterized as abbreviate abstracts packets with common activated acknowledgements.29 This blazon of cartage reduces the ability of the link, due to aerial from packet parsing and affected interrupts (either in the device's host interface or the PC's CPU.) Being a agreement for accessories affiliated to the aforementioned printed ambit board, it does not crave the aforementioned altruism for manual errors as a agreement for advice over best distances, and thus, this accident of ability is not accurate to PCIe.
